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1

Design of a DNA-based reversible arithmetic and logic unit

Sarker, Ankur, Hasan Babu, Hafiz Md., Rashid, Sarker Md Mahbubur

Journal:

IET Nanobiotechnology

Year:

2015

Language:

english

File:

PDF, 1.15 MB

english, 2015

2

Efficient approaches for designing reversible Binary Coded Decimal adders

Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu

Journal:

Microelectronics Journal

Year:

2008

Language:

english

File:

PDF, 376 KB

english, 2008

3

[IEEE 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) - Dhaka, Bangladesh (2015.12.19-2015.12.20)] 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) - Design of compact reversible online testable ripple carry adder

Bose, Avishek, Babu, Hafiz Md. Hasan, Gupta, Shalini

Year:

2015

Language:

english

File:

PDF, 592 KB

english, 2015

4

Reversible and DNA Computing ||

Babu, Hafiz Md. Hasan

Year:

2020

File:

PDF, 18.15 MB

2020

5

Design of a compact reversible binary coded decimal adder circuit

Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury

Journal:

Journal of Systems Architecture

Year:

2006

Language:

english

File:

PDF, 222 KB

english, 2006

6

[IEEE 2013 IEEE International Symposium on Circuits and Systems (ISCAS) - Beijing (2013.5.19-2013.5.23)] 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) - Efficient approaches to design a reversible floating point divider

Jamal, Lafifa, Babu, Hafiz Md Hasan

Year:

2013

Language:

english

File:

PDF, 871 KB

english, 2013

7

[IEEE 2014 IEEE International Symposium on Circuits and Systems (ISCAS) - Melbourne VIC, Australia (2014.6.1-2014.6.5)] 2014 IEEE International Symposium on Circuits and Systems (ISCAS) - A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid

Sarker, Ankur, Hasan Babu, Hafiz Md., Islam, Md. Saiful

Year:

2014

Language:

english

File:

PDF, 526 KB

english, 2014

8

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - A compact representation of a quantum controlled ternary barrel shifter

Lisa, Nusrat Jahan, Babu, Hafiz Md. Hasan

Year:

2015

Language:

english

File:

PDF, 1.09 MB

english, 2015

9

[IEEE 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - Montréal, QC, Canada (2016.5.22-2016.5.25)] 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - A LUT-based matrix multiplication using neural networks

Sworna, Zarrin Tasnim, Haque, Mubin Ul, Babu, Hafiz Md. Hasan

Year:

2016

Language:

english

File:

PDF, 669 KB

english, 2016

10

[IEEE 2010 23rd International Conference on VLSI Design: concurrently with the 9th International Conference on Embedded Systems Design (VLSID) - Bangalore, India (2010.01.3-2010.01.7)] 2010 23rd International Conference on VLSI Design - An Efficient Design of a Reversible Barrel Shifter

Hashmi, Irina, Babu, Hafiz Md. Hasan

Year:

2010

Language:

english

File:

PDF, 293 KB

english, 2010

11

Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis

Shamsujjoha, Md., Hasan Babu, Hafiz Md., Jamal, Lafifa

Journal:

Microelectronics Journal

Year:

2013

Language:

english

File:

PDF, 2.48 MB

english, 2013

12

An efficient approach to design a reversible control unit of a processor

Jamal, Lafifa, Masbaul Alam, Md., Hasan Babu, Hafiz Md.

Journal:

Sustainable Computing: Informatics and Systems

Year:

2013

Language:

english

File:

PDF, 1.15 MB

english, 2013

13

[IEEE 2008 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTVS) - Cambridge, MA, USA (2008.10.1-2008.10.3)] 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems - Minimization of CTS of k-CNOT Circuits for SSF and MSF Model

Ibrahim, Muhammad, Chowdhury, Ahsan Raja, Babu, Hafiz Md. Hasan

Year:

2008

Language:

english

File:

PDF, 353 KB

english, 2008

14

[IEEE 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems - Pune, India (2013.01.5-2013.01.10)] 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems - A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors

Shamsujjoha, Md., Babu, Hafiz Md. Hasan

Year:

2013

Language:

english

File:

PDF, 393 KB

english, 2013

15

[IEEE 2013 IEEE 26th International SoC Conference (SOCC) - Erlangen, Germany (2013.09.4-2013.09.6)] 2013 IEEE International SOC Conference - A novel approach to design a reversible shifter circuit using DNA

Ahmed, Tanvir, Sarker, Ankur, Sharif, Mohd. Istiaq, Rashid, S. M. Mahbubur, Rahman, Md. Atiqur, Babu, Hafiz Md. Hasan

Year:

2013

Language:

english

File:

PDF, 1.21 MB

english, 2013

16

Approach to design a compact reversible low power binary comparator

Hasan Babu, Hafiz Md., Sasao, Tsutomu, Sarwar, Sheikh Muhammad, Jamal, Lafifa, Saleheen, Nazir

Journal:

IET Computers & Digital Techniques

Year:

2014

Language:

english

File:

PDF, 591 KB

english, 2014

17

[IEEE 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication (ICEIEC) - Beijing, China (2013.11.15-2013.11.17)] 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication - A compact realization of a reversible quantum n-to-2n decoder

Lisa, Nusrat Jahan, Hasan Babu, Hafiz Md.

Year:

2013

Language:

english

File:

PDF, 648 KB

english, 2013

18

[IEEE 2013 IEEE 26th International SoC Conference (SOCC) - Erlangen, Germany (2013.09.4-2013.09.6)] 2013 IEEE International SOC Conference - An optimal design of a fault tolerant reversible multiplier

Jamal, Lafifa, Rahman, Md. Mushfiqur, Babu, Hafiz Md. Hasan

Year:

2013

Language:

english

File:

PDF, 1.64 MB

english, 2013

19

[IEEE Proceedings. Euromicro Symposium on Digital System Design - Belek-Antalya, Turkey (2003.09.1-2003.09.6)] Euromicro Symposium on Digital System Design, 2003. Proceedings. - Reversible logic synthesis for minimization of full-adder circuit

Hafiz Md Hasan Babu,, Md Rafiqul Islam,, Ahsan Raja Chowdhury,, Syed Mostahed Ali Chowdhury,

Year:

2003

Language:

english

File:

PDF, 261 KB

english, 2003

20

[IEEE 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) - Leicester, United Kingdom (2014.7.14-2014.7.17)] 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) - A compact realization of an n-bit quantum carry skip adder circuit with optimal delay

Lisa, Nusrat Jahan, Babu, Hafiz Md. Hasan

Year:

2014

Language:

english

File:

PDF, 652 KB

english, 2014

21

[IEEE 2013 IEEE 26th International SoC Conference (SOCC) - Erlangen, Germany (2013.09.4-2013.09.6)] 2013 IEEE International SOC Conference - An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

Babu, Hafiz Md. Hasan, Jamal, Lafifa, Saleheen, Nazir

Year:

2013

Language:

english

File:

PDF, 1.14 MB

english, 2013

22

[IEEE 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Paris, France (2014.7.8-2014.7.10)] 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Minimization of a reversible quantum 2n-to-n BCD priority encoder

Lisa, Nusrat Jahan, Hasan Babu, Hafiz Md.

Year:

2014

File:

PDF, 321 KB

2014

23

[IEEE 2009 International Conference on Signal Processing Systems - Singapore (2009.05.15-2009.05.17)] 2009 International Conference on Signal Processing Systems - Efficient Design of Shift Registers Using Reversible Logic

Nayeem, Noor Muhammed, Hossain, Md. Adnan, Jamal, Lafifa, Babu, Hafiz Md. Hasan

Year:

2009

Language:

english

File:

PDF, 389 KB

english, 2009

24

[IEEE Bioengineering (BIBE) - Taichung, Taiwan (2011.10.24-2011.10.26)] 2011 IEEE 11th International Conference on Bioinformatics and Bioengineering - Realization of Reversible Logic in DNA Computing

Sarker, Ankur, Ahmed, Tanvir, Rashid, S.M. Mahbubur, Anwar, Shahed, Jaman, Lafifa, Tara, Nazma, Alam, Md. Masbaul, Babu, Hafiz Md. Hasan

Year:

2011

Language:

english

File:

PDF, 224 KB

english, 2011

25

[IEEE 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems - Pune, India (2013.01.5-2013.01.10)] 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems - Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter

Shamsujjoha, Md., Babu, Hafiz Md. Hasan, Jamal, Lafifa, Chowdhury, Ahsan Raja

Year:

2013

Language:

english

File:

PDF, 587 KB

english, 2013

26

[IEEE 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) - Cancun, Mexico (2009.08.2-2009.08.5)] 2009 52nd IEEE International Midwest Symposium on Circuits and Systems - Novel reversible division hardware

Nayeem, Noor Muhammed, Hossain, Adnan, Haque, Mutasimul, Jamal, Lafifa, Babu, Hafiz M. Hasan

Year:

2009

Language:

english

File:

PDF, 665 KB

english, 2009

27

[IEEE 2013 IEEE 13th International Conference on Bioinformatics and Bioengineering (BIBE) - Chania, Greece (2013.11.10-2013.11.13)] 13th IEEE International Conference on BioInformatics and BioEngineering - Implementation of reversible multiplier circuit using Deoxyribonucleic acid

Sarker, Ankur, Sharif, Mohd. Istiaq, Rashid, S. M. Mahbubur, Babu, Hafiz Md. Hasan

Year:

2013

Language:

english

File:

PDF, 657 KB

english, 2013

28

[IEEE 21st International Conference on VLSI Design (VLSID 2008) - Hyderabad, India (2008.01.4-2008.01.8)] 21st International Conference on VLSI Design (VLSID 2008) - A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

Biswas, Ashis Kumer, Hasan, Md. Mahmudul, Hasan, Moshaddek, Chowdhury, Ahsan Raja, Babu, Hafiz Md. Hasan

Year:

2008

Language:

english

File:

PDF, 741 KB

english, 2008

29

[IEEE 2015 28th International Conference on VLSI Design (VLSID) - Bangalore, India (2015.1.3-2015.1.7)] 2015 28th International Conference on VLSI Design - Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming

Lisa, Nusrat Jahan, Babu, Hafiz Md. Hasan

Year:

2015

Language:

english

File:

PDF, 400 KB

english, 2015

30

Optimized fault tolerant designs of the reversible barrel shifters using low power MOS transistors

Shamsujjoha, Md., Hossain, Fahmida, Ali, Md. Nawab Yousuf, Babu, Hafiz Md. Hasan

Journal:

Journal of Computational Electronics

Year:

2015

Language:

english

File:

PDF, 2.53 MB

english, 2015

31

[IEEE 2008 11th International Conference on Computer and Information Technology (ICCIT) - Khulna, Bangladesh (2008.12.24-2008.12.27)] 2008 11th International Conference on Computer and Information Technology - On the minimization of complete test set of reversible k-CNOT circuits for Stuck-at Fault model

Ibrahim, Muhammad, Chowdhury, Ahsan Raja, Babu, Hafiz Md. Hasan

Year:

2008

Language:

english

File:

PDF, 2.43 MB

english, 2008

32

[ACM Press the great lakes symposium - Salt Lake City, Utah, USA (2012.05.03-2012.05.04)] Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 - An efficient approach for designing and minimizing reversible programmable logic arrays

Mitra, Sajib Kumar, Jamal, Lafifa, Kaneko, Mineo, Hasan Babu, Hafiz Md.

Year:

2012

Language:

english

File:

PDF, 870 KB

english, 2012

33

[ACM Press the 2014 IEEE/ACM International Symposium - Paris, France (2014.07.08-2014.07.10)] Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '14 - Minimization of a reversible quantum 2 n -to-n BCD priority encoder

Lisa, Nusrat Jahan, Babu, Hafiz Md. Hasan

Year:

2014

File:

PDF, 733 KB

2014

34

[IEEE 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Montpellier, France (2015.7.8-2015.7.10)] 2015 IEEE Computer Society Annual Symposium on VLSI - Design and Implementation of a Reversible Central Processing Unit

Jamal, Lafifa, Babu, Hafiz Md. Hasan

Year:

2015

Language:

english

File:

PDF, 164 KB

english, 2015

35

[IEEE 2015 IEEE International Symposium on Multiple-Valued Logic (ISMVL) - Waterloo, ON, Canada (2015.5.18-2015.5.20)] 2015 IEEE International Symposium on Multiple-Valued Logic - Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing

Lisa, Nusrat Jahan, Babu, Hafiz Md. Hasan

Year:

2015

Language:

english

File:

PDF, 409 KB

english, 2015

36

Synthesis of reversible PLA using products sharing

Tara, Nazma, Babu, Hafiz Md. Hasan

Journal:

Journal of Computational Electronics

Year:

2016

Language:

english

File:

PDF, 1.41 MB

english, 2016

37

Design of a compact reversible fault tolerant division circuit

Babu, Hafiz Md. Hasan, Mia, Md. Solaiman

Journal:

Microelectronics Journal

Year:

2016

Language:

english

File:

PDF, 2.23 MB

english, 2016

38

[IEEE 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Kolkata, India (2016.1.4-2016.1.8)] 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - An Improved Design of a Reversible Fault Tolerant LUT-based FPGA

Haque, Mubin Ul, Sworna, Zarrin Tasnim, Babu, Hafiz Md. Hasan

Year:

2016

Language:

english

File:

PDF, 900 KB

english, 2016

39

[IEEE 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Kolkata, India (2016.1.4-2016.1.8)] 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Logic Synthesis in Reversible PLA

Tara, Nazma, Babu, Hafiz Md. Hasan, Matin, Nawshi

Year:

2016

Language:

english

File:

PDF, 257 KB

english, 2016

40

Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array

Tara, Nazma, UlHaque, Mubin, Sworna, Zarrin Tasnim, Biswas, Ashis Kumar, Hasan Babu, Hafiz Md.

Journal:

IET Circuits Devices & Systems

Year:

2016

Language:

english

File:

PDF, 1.01 MB

english, 2016

41

[IEEE 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) - Dhaka, Bangladesh (2015.12.19-2015.12.20)] 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) - An efficient approach to design a compact reversible programmable logic array

Tara, Nazma, Jamal, Lafifa, Babu, Hafiz Md. Hasan

Year:

2015

Language:

english

File:

PDF, 455 KB

english, 2015

42

[IEEE 2015 18th International Conference on Computer and Information Technology (ICCIT) - Dhaka, Bangladesh (2015.12.21-2015.12.23)] 2015 18th International Conference on Computer and Information Technology (ICCIT) - Optimized designs of reversible fault tolerant BCD adder and fault tolerant reversible carry skip BCD adder

Bose, Avishek, Babu, Hafiz Md. Hasan

Year:

2015

Language:

english

File:

PDF, 735 KB

english, 2015

43

Cost-efficient design of a quantum multiplier–accumulator unit

Babu, Hafiz Md. Hasan

Journal:

Quantum Information Processing

Year:

2017

Language:

english

File:

PDF, 2.84 MB

english, 2017

44

[IEEE 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Bochum, Germany (2017.7.3-2017.7.5)] 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem

Sworna, Zarrin Tasnim, Haque, Mubin Ul, Babu, Hafiz Md. Hasan, Jamal, Lafifa, Biswas, Ashis Kumer

Year:

2017

Language:

english

File:

PDF, 671 KB

english, 2017

45

[IEEE 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Bochum, Germany (2017.7.3-2017.7.5)] 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Area and Delay Efficient Design of a Quantum Bit String Comparator

Babu, Hafiz Md. Hasan, Jamal, Lafifa, Dibbo, Sayanton Vhaduri, Biswas, Ashis Kumer

Year:

2017

Language:

english

File:

PDF, 559 KB

english, 2017

46

Efficient Techniques for Fault Detection and Correction of Reversible Circuits

Babu, Hafiz Md. Hasan, Mia, Md. Solaiman, Biswas, Ashis Kumer

Journal:

Journal of Electronic Testing

Year:

2017

Language:

english

File:

PDF, 1.04 MB

english, 2017

47

Power Efficient Optimum Design of the Reversible Plessey Logic Block of a Field-Programmable Gate Array

Tara, Nazma, Hasan Babu, Hafiz Md., Jamal, Lafifa

Journal:

Sustainable Computing: Informatics and Systems

Year:

2017

Language:

english

File:

PDF, 2.71 MB

english, 2017

48

A Fast FPGA-Based BCD Adder

Ul Haque, Mubin, Sworna, Zarrin Tasnim, Hasan Babu, Hafiz Md., Biswas, Ashis Kumer

Journal:

Circuits, Systems, and Signal Processing

Year:

2018

Language:

english

File:

PDF, 2.47 MB

english, 2018

49

[IEEE 2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) - Dehradun (2017.12.18-2017.12.19)] 2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) - Nanotechnology-Based Efficient Fault Tolerant Decoder in Reversible Logic

Tara, Nazma, Sufian, Md. Kamal Ibne, Babu, Hafiz Md. Hasan

Year:

2017

Language:

english

File:

PDF, 960 KB

english, 2017

50

Reversible and DNA Computing || Bibliography

Babu, Hafiz Md. Hasan

Year:

2020

File:

PDF, 118 KB

2020

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